IDT82V3202NLG【PDF 34/117 页】IC PLL WAN EBU SGL 68-VFQFPN

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IDT82V3202

EBU WAN PLL

Functional Description

September 11, 2009

3.6

DPLL INPUT CLOCK SELECTION

The EXT_SW bit and the T0_INPUT_SEL[3:0] bits determine the

input clock selection, as shown in Table 6:

External Fast selection is done between IN1_CMOS and

IN2_CMOS.

Forced selection is done by setting the related registers.

Automatic selection is done based on the results of input clocks qual-

ity monitoring and the related registers configuration.

The selected input clock is attempted to be locked by T0 DPLL.

3.6.1

EXTERNAL FAST SELECTION

In External Fast selection, only IN1_CMOS and IN2_CMOS are

available for selection. Refer to Figure 6. The results of input clocks

quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring)

do not affect input clock selection.

The T0 input clock selection is determined by the FF_SRCSW pin

after reset (this pin determines the default value of the EXT_SW bit dur-

ing

reset,

refer

Chapter 2

Description),

the

IN1_CMOS_SEL_PRIORITY[3:0]

bits

and

the

IN2_CMOS_SEL_PRIORITY[3:0] bits, as shown in Figure 6 and

Table 7:

Figure 6. External Fast Selection

Table 6: Input Clock Selection

Control Bits

Input Clock Selection

EXT_SW

T0_INPUT_SEL[3:0]

don’t-care

External Fast selection

other than 0000

Forced selection

0000

Automatic selection

FF_SRCSW pin

IN1_CMOS

IN2_CMOS

IN1_CMOS_SEL_PRIORITY[3:0] bits

IN2_CMOS_SEL_PRIORITY[3:0] bits

attempted to be

locked in T0 DPLL

Table 7: External Fast Selection

Control Pin & Bits

the Selected Input Clock

FF_SRCSW (after reset)

IN1_CMOS_SEL_PRIORITY[3:0]

IN2_CMOS_SEL_PRIORITY[3:0]

high

other than 0000

don’t-care

IN1_CMOS

low

don’t-care

other than 0000

IN2_CMOS

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